Direct current signal isolator providing a close replica of wave shape

ABSTRACT

A circuit providing information regarding the magnitude and polarity of signals in an electrical system. The signals may be A.C., D.C., asymmetrical, or of a pulse nature. A flip-flop drives a saturable reactor &#39;&#39;&#39;&#39;trigger&#39;&#39;&#39;&#39; winding alternately with opposite voltage polarities, and pulses generated by the saturation phenomenon of the trigger reactor control the flipflop to reverse the voltage upon saturation. A second nonsaturating reactor &#39;&#39;&#39;&#39;gate&#39;&#39;&#39;&#39; winding, not magnetically coupled to the saturating core, is also driven by the flip-flop on a minor hysteresis loop. A D.C. input signal winding is wound simultaneously on both cores. The output signal is obtained from the &#39;&#39;&#39;&#39;gate&#39;&#39;&#39;&#39; winding and is a close replica of the input signal wave form.

United States Patent [191 Risberg DIRECT CURRENT SIGNAL ISOLATOR PROVIDING A CLOSE REPLICA OF WAVE 3,746,888 7/1973 Wentworth 307/88 MP SHAPE Primary Examiner-Stanley M. Urynowicz, Jr. [75] Inventor: Robert L. Risberg, Brookfield, Wis. l z Agent or Firm-H Rather;

u 10 [73] Assignee: Cutler-Hammer, Inc., Milwaukee,

57 ABSTRACT [22] filed: 1973 A circuit providing information regarding the magni- [21] Appl. No.: 341,564 tude and polarity of signals in an electrical system. The signals may be A.C., D.C., asymmetrical, or of a 52 U.S. Cl 307/88 MP, 307/282, 321/25, B l i F- P a satllrablel 328/21 tr gger win mg a ternate y w1t opposite vo tage po- [511 Int Cl 02m 5/10 larities, and pulses generated by the saturation phe- [vislw Field of Search 307/282, 88 LC 88 R, 88 MB; nomenonhof the trigger reactor control Athe flip-310p to 328/21 33 321/25 26 47 reverse t e v0 tage upon saturation. secon nonsaturating reactor gate winding, not magnetically [56] References Cited coupled to the saturating core, is also driven by the flip-flop on a minor hysteresis loop. A DC. input sig- UNITED STATES PATENTS nal winding is wound simultaneously on both cores. 2,603,768 7/1952 Trindle 321/47 The output signal is obtained from the gate winding a S l 1 gt and is a close replica of the input signal wave form. 0 m1 7 3,673,487 6/1972 Hendrickson 321/47 11 Claims, 5 Drawing Figures Fe FLIP-FLOP A 2 v I I f .121 e2 5; 5220 I C1; C2) 'g gal 2f! I C 4 Jix I pi n2 7 or mm our 0 212%; q I J 054E DIRECT CURRENT'SIGNAL ISOLATOR PROVIDING A CLOSE REPLICA OF WAVE SHAPE BACKGROUND OF THE INVENTION Signal isolators have been known heretofore. One common type is the current transformer wherein a secondary winding having many turns picks up a signal from the primary which may be a single power conductor passing through the secondary winding. Another type is the magnetic amplifier; another is the transductor. While these devices'have been useful for their intended purpose, this invention relates to improvements 'thereover.

SUMMARY OF THE INVENTION This invention relates to a universal signal isolator providing a close replica of wave shapes, and produces polarity as well as amplitude information. This accurate informationwith respect to the magnitude of signals in a system is required for a number of applications, for

example, for use in a level detector for control pur- BRIEF DESCRIPTION OF THE DRAWINGS FIG. I is a circuit diagram showing the signal isolator constructed in accordance with the invention;

FIG. 2 is a graph showing by way of hysteresis loops the relative functions of the'trigger and gate windings of the circuit of FIG. 1;

FIG. 3 is a graph showing the wave forms of currents in the trigger and gate windings;

FIG. 4 shows the self-saturating magnetic inverter windings of FIG. 1 in more detail; and

FIG; shows a schematic of the gate core.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, there is shown a signal isolator system according to the invention.

This system is supplied with operating power from a center-tapped direct current source. For this purpose, the positive side of the source is connected to conductor 2 and from the latter through normally-open power relay contact PR to positive supply conductor 4. The center tap of the source is connected to zero voltage conductor 6 and the negative side thereof is connected to negative conductor 8.

The system is provided with a self-saturating magnetic inverter comprising a flip-flop circuit, driver transistors and a saturable reactor for controlling the inverting function.

In addition, the system is provided with a gate reactor that is non-saturating for providing the output signal.

This flip-flop circuit comprises, as shown at the lefthand portion of FIG. 1, a pair of transistors Q1 and Q2 of the N-P-N conductivity type. The collectors of these transistors receive voltage from positive conductor 4 through load resistors R1 and R2, respectively, while their emitters are connected directly to zero conductor 6. Capacitors C l and C2 are cross-coupled between the collectors and bases of transistors Q1 and Q2, respectively, to provide fast switching of the flip-flop. Transient suppression capacitors C3 and C4 are connected from the bases of transistors Q1 and Q2, respectively, to zero conductor 6. Unidirectional diodes Dl'and D2 are connected from zero conductor 6 to the bases of transistors Q1 and Q2, respectively, to limit any reverse voltage on the base-emitter junctions of the two transistors.

From the foregoing, it will be apparent that only one transistor of the flip-flop circuit can conduct at a time. When one transistor turns on, the voltage at its collector drops to a voltage level near zero voltage which acts through the corresponding cross-coupling-capacitor to reduce the voltage proportionally on the base of the other transistor to maintain it turned off.

A pair of switching transistors are connected to the collectors of the flip-flop transistors. For this purpose, positive voltage conductor 4 is connected through the emitter-base junction of a P-N-P output driver transistor Q3, a zener diode ZDl and a current limiting resistor R3 to the collector of transistor Q]. In a similar manner, conductor 4 is connected through a load resistor R4, the emitter-base junction of a P-N-P output driver transistor Q4, a zener diode ZD2 and a current limiting resistor R5 to the collector of transistor 02.

A resistor R6 is connected across the emitter-base junction of transistor 03 to provide a path for transistor leakage current. A resistor R7 is similarly connected across resistor R4 and the emitter-base junction of transistor Q4. The collector of transistor Q3 is connected through voltage divider resistors R8 and R9 in series to negative voltage conductor 8. The collector of transistor 04 is connected through voltage dropping resistor R10 to zero voltage conductor 6.

Transistors Q3 and Q4 control switching transistors Q5 and 06, respectively, to cause voltage excitation of the trigger and gate wndings alternately in opposite directions. For this purpose, the junction between resis- Switching transistors 05 and Q6 alternately close excitation paths in opposite directions through both the trigger and gate windings. For this purpose, a first trigger circuit extends from positive conductor 4 through resistor Rll, static balance potentiometer POT, dynamic balance adjusting variable resistor VR, trigger winding T1, resistor R12 and the collector-emitter junction of transistor O5 to negative conductor 8. Excitation in this path will magnetize the trigger core in one direction. A second trigger circuit extends from positive conductor 4 through the emitter-collector junction of transistor Q6, resistor R13, trigger winding Tl, variable resistor VR, potentiometer POT, and resistor R14 to negative conductor 8. Voltage excitation via this path will altemately magnetize the trigger core in the opposite direction.

As aforementioned, these switching transistors also close excitation paths through the gate winding. For this purpose, a first gate circuit extends from positive conductor 4 through resistor R15, gate winding G, resistor R12 and the collector-emitter junction of transistor O to negative conductor 8. Excitation via this path will magnetize the gate core in one direction at the same time as the trigger core is magnetized in one direction as aforementioned. A second gate circuit extends from positive conductor 4 through the emittercollector junction of transistor Q6, resistor R13, gate winding G, and resistor R16 to negative conductor 8. Excitation via this path will magnetize the gate core in the opposite direction at the same time as the trigger winding is, magnetized in the opposite direction as aforementioned. In other words, the trigger and gate windings are energized in parallel by the switching transistors, first in one direction and then in the opposite direction, respectively, nagnetization progressing as the time integral of the'voltage across the excitation windmgs.

Shunt paths are provided at the switching transistors to permit reverse current flow in parallel therewith to allow bilateral behavior of the switch. As will be explained, voltages in the trigger and gate windings will cause current to flow in the opposite direction of the excitation voltage when the signal is of a given polarity. For this purpose, a diode D3 is connected from the emitter to the collector of transistor Q5, and a diode D4 is connected from the collector to the emitter of transistor 06.

The input signal to the system, which is to be reproduced in an isolated and close replica manner at the system output, is applied from a signal source e through a current limiting resistor R17 to signal winding S. This resistor is chosen to be of sufficient value such that the signal will appear as a current source. Induced voltages in the signal winding will have trivial effect on signal current. By contrast, the excitation windings are fed from an approximate voltage source. While one signal source and winding is shown, it will be apparent that more than one signal source and winding may be used and the signals will be added algebraically in the output. The signal winding is wound on both the trigger and gate cores as schematically shown in FIG.

The output is taken from the gate reactor. For this purpose, the junction between the gate winding and voltage divider resistors R and R16 is connected through a current limiting output resistor R18 to output terminal OT which provides an output voltage e relative to ground.

An alternative output E (ALT.) may be taken from the trigger reactor as shown in dotted lines in FIG. 1. The excitation spikes appear in this output as shown in FIG. 3(a) and require considerable filtering. For this output, an alternate output resistor R19 is connected from the junction between the trigger winding and variable resistor VR to zero conductor 6, and the alternate output terminals are connected across this resistor.

The flip-flop reinforcing pulses are taken from trigger winding T]. For this purpose, a circuit extends from positive conductor 4 through resistor R20 and diode D5 in its forward,-Iow impedance direction to zero voltage conductor 6. The junction between this resistor and 4 diode is connected through one secondary winding T2 and current limiting resistor R21 to the base of flip-flop transistor Q1. This same junction is also connected through another secondary winding T3 and current limiting resistor R22 to the base of flip-flop transistor T2. As shown by the dots adjacent these secondary. windings, they are arranged to provide currents of opposite polarity (by 180) to the respective transistors in the flip-flop to reinforce their conduction alternately.

wound on the trigger winding core. I 1

OPERATION When power is applied to the system by closingv contact PR, one of the transistors in the flip-flop will turn on and the other will turn off. Current will start to flow through both transistors but due to an inherent unbalance in the circuit, the current in one transistor will increase over that of the other. Let is be assumed that transistor Q1 conducts more. The resultant decrease in its collector voltage is coupled through capacitor C1 to the base of transistor Q2. This reduced voltage at the base reduces the current through transistor Q2 and its collector voltage rises. This rise in voltage incoupled through capacitor C2 to the base of the transistor 01 to further increase the flow of current therethrough. This causes the collector voltage of transistor O1 to decrease even more and the base of transistor O2 is driven more negative. As a result of this regenerative action, transistor O1 isdriven to saturation almost instantaneously and, just as quickly, transistor O2 is cut off.

When the increasing voltage across resistor R1 as transistor Q1 turns on exceeds the breakover value of zener diode ZDl, transistor O3'turns on, turning on transistor Q5. Zener diode ZDl is included between one side of the flip-flop and driver transistor O3 so that this driver transistor will ignore the slow rate of change of current that exists at the onset of the switching from one side of the flip-flop to the other. Once the switching has gotten started, the rate of change is very fast. At this point, the load applied by driver transistor 03 can be tolerated. The zener diode changes from conducting to non-conducting and vice versa very quickly, providing a well-formed square wave at the collector of transistor Q5.

Zener diode ZD2 is included between the other side of the flip-flop and driver transistor Q4 for a similar purpose.

When switching transistor O5 is turned on as aforesaid, voltage is applied in the left-hand direction across trigger winding T1 and gate winding G. The trigger winding induces a voltage in winding T2 to cause a current to flow from the right-handend thereof through resistor R21 into the base of transistor 01. This reinforces the drive to the side of the flip-flop that is turned on.

When the trigger reactor saturates as shown in FIG. 2 the cross-coupled capacitors Cl and C2 in the flipflop will have reached steady state before this time.

This saturation terminates the current drive to flip-flop transistor Q1. As a result, transistor Q1 will start to turn off with a consequent rise in the voltage applied from its collector to the base of transistor Q2, causing the latter to turn on. Turn on of transistor Q2 will cause operation of transistors Q4 and Q6, as hereinbefore described in connection with transistors Q3 and O5, to excite the trigger and gate windings in the opposite direction by applying voltage in the right-hand direction.

Conduction of transistor Q2 is now reinforced by current flow into its base from'winding T3.

The flip-flop then continues to be controlled by the saturable reactor trigger winding to generate a squarewave voltage that is applied to both the trigger and gate windings.

Connection of a resistance across signal winding S will cause the gate winding current to increase as secondary current flows by transformer action in the signal winding and resistor. The impedance of the signal source reflected to the gate winding circuit is set high to control the amount of this current, which appears as ripple in the output. The signal source is thus made to approximate a current source. If a signal is present, the current in the gate winding will be proportional to the magnetizing current plus the signal current, as shown in FIG. 3(b), on one half-cycle and the signal current minus the magnetizing current on the next half-cycle. The gate winding behaves as the primary when the polarities are additive and as a secondary when it is overridden by the signal source on the next half-cycle. This can be seen in the FIG. 5 schematic. For example, when e applies a positive voltage to the dotted end of the gate winding, gate current will jump to a value proportional to the current already flowing in the signal winding plus a gate magnetization current. During the next half-cycle, however, the gate voltage positive is applied to the undotted end of the gate winding. Now both the gate and the signal tend to cause current to flow .to magnetize the core in the same direction. Which winding will behave as primary will be determined by the volts per turn on that winding. However, since the signal is a current source, it will induce any voltage, whereas the gate is limited and becomes the secondary. v

The magnetizing current thus averages out to zero in the gate winding and the signal current is detected at the output terminals as shown in FIG. 3(b).

To obtain a nearly ripple-free signal, i.e., less than one percent, a second reactor (gate winding reactor) is used with a greater number of gate turns not magnetically coupled to the saturating (trigger winding) core. This second core is operated on a minor hysteresis loop as shown in FIG. 2, reducing its magnetizing current. The signal windings are wound through both core windows simultaneously, hence the signal is detected in the second (gate) winding. However, the signal source is kept a current source as hereinbefore described so that no coupling exists between the trigger and gate windmgs.

To avoid dissymmetry in flux due to power supply im balance (to a large degree this is self-corrected by the saturating reactor, but enough imbalance due to secondary effects results to cause one side saturation on the non-saturating gate core), it is desirable to let zero voltage point for each reactor float as shown in FIG. 1. This is afforded by connecting the gate winding between voltage divider resistors 15 and 16, and connecting the trigger winding to an intermediate point between voltage divider resistors R11 and R14. Any reasonable (plus or minus 20 percent or the like) power supply imbalance is nulled out. The output voltage might have a slight offset due to power supply differences or the like. This is not a serious problem since this output voltage e would normally feed an operational amplifier in a differential mode or a transistor differential amplifier, either of which will reject common mode offset.

The static balance potentiometer POT insures that at no load the excitation to the cores is balanced. This can be seen easily by observing the output voltage and adjusting the static balance potentiometer so that the ripple is equal and without saturation of the gate core at no load.

The rated signal ampere-turns is times greater than the no load or excitation ampere-turns. Therefore, there is a large D.C. component of current in the excitation (or output) coils G and T1.

The gate coil G typically has 1.5 to 2 times the turns of the trigger coil TI on the other core. This is to insure that the flux swing on the gate core is less than the flux swing on the saturating trigger since A l/n I edt where n is the number of turns, and e is the applied voltage, which is the same on each core. The saturated reactance of reactor T1 is not the sameas the reactance of reactor G at the flat (or top and bottom) of its hysteresis loop as shown in FIG. 2. However, the saturated time constant of reactor Tl can be made the same as the reactor G flat portion time constant. If these time constants are not approximately equal, the excitation volt-seconds in the presence of a'large signal will not be equal for the two cores.

The dynamic balance is set by using a very fast rising large signal such as an SCR firing into a resistor. The rise time would be on the order of a microsecond. The dynamic balance variable resistor VR then is adjusted so that the output voltage has no excitation spikes under dynamic (or loaded) conditions (rated signal, fast rising, etc.).

The idea is to allow the trigger reactor to respond as a conventional signal isolator and to use its switching instants to reverse the excitation on both cores. Thus, the best response is obtainted. Ripple is on the order of 1 percent and speed is approximately 1 microsecond.

The signal has to be applied to the trigger reactor so that the latter will switch in time to avoid saturating the gate core. The signal has to be applied to the gate reactor so that it will be present in the output.

While the system hereinbefore described is effectively adapted to fulfill the objects stated, it is to be understood that the invention is not intended to be confined to the particular preferred embodiment of universal signal isolator providing a close replica of wave shape disclosed, inasmuch as it is susceptible of various modifications without departing from the scope of the appended claims.

I claim:

1. A signal isolator comprising:

a direct current source;

a self-saturating magnetic inverter comprising:

a trigger reactor;

inverting switching means supplied from said source for applying alternating voltage to said trigger reactor;

n inputsignal source; i

ciose'replicaxof said'input signal. T n 2.The inventiondefinedinclaim l whe re in said in-f 1 a qua' sv a v :v {of alternate opposite polar ty control o means c'ouplingsaid D.C input signal source to said I Q trigger reactor whereby said DC. input; signal I; along withjsaid alternatingvoltageexcites said trig- 3 larity'direcitions and means coupled to said trigger reactor for driving said in'vertingswi'tching' means; 7 ands'aid' signal isolator further comprising: 'a'gatereactor';

said *coupling'rneans comprising means'also coupling 1 said" D.C. input signal to 's'aid gate-reactor; means connecting said gate reactor to said inverting switching means to "therefrom; x t said g'atereactor comprisingmeans responsive to said alternating voltage and said input signal for operati ng ona minor, non saturating hysteresis loop to' provide an output signal isolated from 'and'being a vertin'gswitching'nieanscomprises: a v I v P l ehe or o e a i trigger-reactor;

and switchin'g means by said souafre wave 'g'er'reactor'to. saturation alternately in opposite po- I receive alternating voltage 2 pulses i pulsejgenerator f r'eXciting'said trigger reactor-.1

3. The in'vention'de'fined iniciairn '1; wherein said inverting switching-means comprises:

a pair of driver transistors alternately operable 'saidflip-jflopcircuit: v

and apairof switching transistors controlled by said 7 driver transistors for connecting said direct current 5' sourceto said trigger reactor alternately in opposite-directions.

'4. The invention defined in claim 1, wherein said trigv ger. and gate reactors comprise:

trigger and gate windings wound on separate iron cores not magnetically coupled to one'another. .5. Theinvention defined in claim 4,]wherein said couplingme'ans comprises: I

9 "a signal windingmagnetically coupled to both the trigger and gate winding cores.

i 6.'The invention defined in claim 1, wherein said gate reactor comprises:

agate windinghavmg more-turns thansaid'trigger winding and being wound on a separate magnetic core not magnetically coupled to said triggerwindin an additive manner;

8; Asignal isolator -providin g an output signal that is a close replicaof'an inputsignal comprising:

a direct-current source; 7 1

' a self-saturating magnetic inverter supplied from said source and. comprising: y a trigger reactor havingjacore I winding thereon and control winding means;

controlled inverting-means suppliedi-from saidsource 1 and controlled by said control windingmeans for ,Fapplyin'gsquare-wave alternating "voltage to "said j W .,,1 'wi di g;',. y and an input isignaljwinding coupled to's'aid trigger eac or for applying a: variable D'.C: input signal 7 current thereto'wherj'ebyperiodicsaturationbf'said';

, i ger r totp t iau s pfii a ipnpfsaid s'el r,

lsaturatingmagnetic inverter; 4.. Wand said signal is lat'or also 'including'meansprovid- -"ing an output signalthat is .a-close replfaofgsaid :variable' inputsignal comprising:-

a gatereactor to which-said input signal winding is also coupled;

saturating magnetic inverterto apply, verse excitation to said gate reactor; 1

I and output signal 'means connected to' said tor." 1 9. The invention defined in claim8, whereinz I said direct current source is acenter-tapped sourcehaving azero voltage center point; v "and said output signal means isconnected to said gate reactor and said zero voltage point whereby power supply imbalance is nulled out.

- l0; The invention defined in claim 8, wherein said I self-saturating magnetic inverter also comprises: v a

means for adjusting the static balanceof said triggerv reactor.

, self-saturatingmagnetic inverter also comprises: v means for adjusting the dynamic balance of said trig. ger reactor. j I,

trigger I means using" the switching instantsofjsaidselfperiodic re.-"

gatereacQ 11. Theinvention defined in claim 18, wherein said 

1. A signal isolator comprising: a direct current source; a self-saturating magnetic inverter comprising: a trigger reactor; inverting switching means supplied from said source for applying alternating voltage to said trigger reactor; a D.C. input signal source; means coupling said D.C. input signal source to said trigger reactor whereby said D.C. input signal along with said alternating voltage excites said trigger reactor to saturation alternately in opposite polarity directions; and means coupled to said trigger reactor for driving said inverting switching means; and said signal isolator further comprising: a gate reactor; said coupling means comprising means also coupling said D.C. input signal to said gate reactor; means connecting said gate reactor to said inverting switching means to receive alternating voltage therefrom; said gate reactor comprising means responsive to said alternating voltage and said input signal for operating on a minor, non-saturating hysteresis loop to provide an output signal isolated from and being a close replica of said input signal.
 2. The invention defined in claim 1, wherein said inverting switching means comprises: a square-wave pulse generator for generating pulses of alternate opposite polarity under control of said trigger reactor; and switching means controlled by said square-wave pulse generator for exciting said trigger reactor.
 3. The invention defined in claim 1, wherein said inverting switching means comprises: a flip-flop circuit; a pair of driver transistors alternately operable by said flip-flop circuit; and a pair of switching transistors controlled by said driver transistors for connecting said direct current source to said trigger reactor alternately in opposite directions.
 4. The invention defined in claim 1, wherein said trigger and gate reactors comprise: trigger and gate windings wound on separate iron cores not magnetically coupled to one another.
 5. The invention defined in claim 4, wherein said coupling means comprises: a signal winding magnetically coupled to both the trigger and gate winding cores.
 6. The invention defined in claim 1, wherein said gate reactor comprises: a gate winding having more turns than said trigger winding and being wound on a separate magnetic core not magnetically coupled to said trigger winding.
 7. The invention defined in claim 1, wherein: said D.C. input signal source comprises means providing a plUrality of input signal components; and said coupling means comprises means coupling said input signal components to said trigger reactor in an additive manner.
 8. A signal isolator providing an output signal that is a close replica of an input signal comprising: a direct current source; a self-saturating magnetic inverter supplied from said source and comprising: a trigger reactor having a core and an A.C. trigger winding thereon and control winding means; controlled inverting means supplied from said source and controlled by said control winding means for applying square-wave alternating voltage to said trigger winding; and an input signal winding coupled to said trigger reactor for applying a variable D.C. input signal current thereto whereby periodic saturation of said trigger reactor core causes operation of said self-saturating magnetic inverter; and said signal isolator also including means providing an output signal that is a close replica of said variable input signal comprising: a gate reactor to which said input signal winding is also coupled; means using the switching instants of said self-saturating magnetic inverter to apply periodic reverse excitation to said gate reactor; and output signal means connected to said gate reactor.
 9. The invention defined in claim 8, wherein: said direct current source is a center-tapped source having a zero voltage center point; and said output signal means is connected to said gate reactor and said zero voltage point whereby power supply imbalance is nulled out.
 10. The invention defined in claim 8, wherein said self-saturating magnetic inverter also comprises: means for adjusting the static balance of said trigger reactor.
 11. The invention defined in claim 8, wherein said self-saturating magnetic inverter also comprises: means for adjusting the dynamic balance of said trigger reactor. 